1. Field of the Invention
The present invention generally relates to data processing systems and more particularly to a lock operation which provides that one user, or a possible plurality of users, of a shared resource is given exclusive use of the shared resource during the period of time in which the shared resource is locked.
In a system having a plurality of devices coupled to a shared resource, an orderly system must be provided by which one of the user devices may obtain the exclusive use of the shared resource for certain types of operations. During this period of exclusive use by one of the devices performing an operation which requires exclusivity, the other device wishes to perform an operation which also requires the exclusive use of the shared resource. This problem becomes more complicated when such devices include, for example, one or more data processors, one or more memory units, and various types of peripheral devices such as magnetic tape storage devices, disk storage devices, card reading equipment and the like.
2. Description of the Prior Art
Various methods and apparatus are known in the prior art for interconnecting such a system. Such prior art systems range from those having common data bus paths to those having special paths between various devices. Such systems also may include a capacity for either synchronous or asynchronous operation in combination with the bus type. Some such systems, independent of the manner in which such devices are connected or operated, require the data processor to control any such data transfer on the bus even though, for example, the transfer may be between devices other than the data processor.
One such structural scheme is shown in U.S. Pat. No. 4,000,485 entitled, "Data Processing System Providing Lock Operation of Shared Resources". This patent describes a data processing system which the shared resource is the main memory which is connected to a common bus over which all transfers to and from device controllers and the central processing unit occur. In this system, if the central processing unit wants to perform a read-modify-write operation on the contents of the locaton in main memory, the data processing system first locks the main memory containing the location to be read and updated so that during the multiple common bus cycles required to first read a memory location and then write it back can be performed uninterrupted without another central processing system or device controller being able to perform another lock operation until the first lock operation has been completed. In this system, although the common bus is an asynchronous bus (any device wishing to make a transfer over the common bus may asynchronously request use of the bus at any time, if the bus is not already in use), there is a priority resolver such that the lock mechanism associated with the shared resource need not be able to handle the case in which the shared resource is being locked by a first requester and a second lock request is made asynchronously from a second requester wishing to perform a lock operation on the shared resource.
With the development of dual ported memories, it has become possible that multiple users may be making simultaneous requests to perform a lock operation on the shared resource. For example, if one port is connected to the common bus which connects device controllers to the main memory and the second port is connected to the central processing unit, it is possible that a device controller may be attempting to perform a lock operation on the main memory at the same time that the central processor wants to perform a lock operation. Therefore, what is needed is a lock mechanism for a shared resource in which competing asynchronous requests from multiple requesters to lock or unlock the shared resource can be handled.